In a semiconductor memory device, a plurality of data buses is used for memory access. One way of achieving fast memory access is by increasing a data transfer speed in the semiconductor memory device, which may be achieved by increasing a number of buses. For example, in a typical Double Data Rate Fourth generation synchronous dynamic random-access memory (DDR4 SDRAM) product, the data transfer speed has been increased by implementing at least 8 bit×8=64 data lines. The 64 data lines have an 8 bit prefetch configuration and data buses of either 8 bit input/output lines (IO×8) with 16 banks configuration or 16 bit Input/Output lines (IO×16) with 8 banks configuration and data bus inversion (DBI) functionality. However, the increase the number of buses tends to result in a larger memory chip size because the plurality of data buses is aligned with intervals in a chip layout in order to avoid undesired noise effects from adjacent buses. Consequently, the increased number of buses with more intervals results in a larger space in the chip layout.
In recent years, in view of increasing a higher data transfer rate of data, technical endeavors need to be made. For example, US 2013/0019044 A1 focuses on arranging bus interface circuits densely in an area in order to accommodate high speed memory data access.